Nonvolatile semiconductor memory device

ABSTRACT

A nonvolatile semiconductor memory device according to an embodiment comprises a control unit, in a data write, determining at least one of: a first requirement that the number of times of a data read on first through n 1 -th pages (where n 1  is an integer of 1 to N−1) of a target block executed after the most recent data erase on the target block, is less than a reference number of times; and a second requirement that the number of memory cells whose threshold voltage is higher than a reference voltage, of a plurality of memory cells of a reference page of n 1 +1-th through N-th pages of the target block, is less than a reference number, and when the determined requirement is satisfied, writing additional data to the n 1 +1-th through N-th pages of the target block.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior U.S. Provisional Application 62/046,421, filed on Sep. 5,2014, the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Field

Embodiments relate to a nonvolatile semiconductor memory device.

2. Description of the Related Art

In the case of a NAND type nonvolatile semiconductor memory device,sometimes, when performing data read on a selected page, a thresholdvoltage of a memory cell of another page of a block to which theselected page belongs ends up varying due to the influence of a readvoltage applied to a word line at this time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of a nonvolatile semiconductormemory device according to a first embodiment.

FIG. 2 is a circuit diagram of a cell array of the nonvolatilesemiconductor memory device according to the same embodiment.

FIG. 3 is a view showing threshold voltage distributions of a memorycell of the nonvolatile semiconductor memory device according to thesame embodiment.

FIG. 4 is a view showing a bias state of the cell array during a programoperation in the nonvolatile semiconductor memory device according tothe same embodiment.

FIG. 5 is a view showing a bias state of the cell array during an eraseoperation in the nonvolatile semiconductor memory device according tothe same embodiment.

FIG. 6 is a view showing a bias state of the cell array during a readoperation in the nonvolatile semiconductor memory device according tothe same embodiment.

FIG. 7 is a view showing a bias state of the cell array during an eraseverify operation in the nonvolatile semiconductor memory deviceaccording to the same embodiment.

FIG. 8 is a view showing a state of transition of the threshold voltagedistributions of the memory cell during a write sequence in thenonvolatile semiconductor memory device according to the sameembodiment.

FIG. 9 is a view showing a write sequence of pages in a data write ofthe nonvolatile semiconductor memory device according to the sameembodiment.

FIG. 10 is a view showing a state of transition of the threshold voltagedistribution of the memory cell during the read operation in thenonvolatile semiconductor memory device according to the sameembodiment.

FIG. 11 is a flowchart of the data write in the nonvolatilesemiconductor memory device according to the same embodiment.

FIG. 12 is a flowchart of a data write in a nonvolatile semiconductormemory device according to a second embodiment.

FIG. 13 is a flowchart of a data write in a nonvolatile semiconductormemory device according to a third embodiment.

DETAILED DESCRIPTION

A nonvolatile semiconductor memory device according to an embodimentcomprises: a cell array including a source line, a plurality of bitlines, a plurality of word lines intersecting the plurality of bitlines, and a plurality of cell strings electrically connected betweenthe source line and the plurality of bit lines, each of the cell stringsbeing configured from a plurality of memory cells connected in series toeach be connected to one of the word lines; and a control unit thatperforms a data write/erase/read on the memory cells, the cell arraybeing divided into a plurality of blocks including a target block, eachof the blocks including first through N-th pages (where N is an integerof 2 or more), each of the pages being configured by a plurality of thememory cells connected to one of the word lines, the control unitexecuting the data write/read in a unit of the page, and executing thedata erase in a unit of the block, and the control unit, in the datawrite, determining at least one of: a first requirement that the numberof times of the data read on first through n1-th pages (where n1 is aninteger of 1 to N−1) of the target block executed after the most recentdata erase on the target block, is less than a reference number oftimes; and a second requirement that the number of memory cells whosethreshold voltage is higher than a reference voltage, of the pluralityof memory cells of a reference page of n1+1-th through N-th pages of thetarget block, is less than a reference number, and when the determinedrequirement is satisfied, writing additional data to the n1+1-th throughN-th pages of the target block.

Nonvolatile semiconductor memory devices according to embodiments willbe described below with reference to the drawings.

First Embodiment

First, an overall configuration of a nonvolatile semiconductor memorydevice according to a first embodiment will be described.

FIG. 1 is a functional block diagram of the nonvolatile semiconductormemory device according to the present embodiment.

This nonvolatile semiconductor memory device is a NAND type flash memoryand comprises: a NAND chip 10; a controller 11 that controls this NANDchip 10; and a ROM fuse 12 that stores various kinds of informationrequired for access to the NAND chip 10.

The NAND chip 10 comprises a cell array 1. The cell array 1 includes aplurality of bit lines extending in a column direction, a plurality ofword lines and a source line extending in a row direction, and aplurality of memory cells selected by the bit line and the word line. Agroup of memory cells selected by one word line configures a page. Adata write/read of the flash memory is performed in a unit of the page.The cell array 1 will be described later.

In addition, the NAND chip 10 comprises a control unit that executes: awrite sequence which is a series of processes for writing data to thememory cell; an erase sequence which is a series of processes forerasing data of the memory cell; and a read sequence which is a sequenceof processes for reading data from the memory cell. The control unitincludes: a row decoder/word line driver 2 a; a column decoder 2 b; apage buffer 3; a row address register 5 a and column address register 5b; a logic control circuit 6; a sequence control circuit 7; a voltagegenerating circuit 8; and an I/O buffer 9.

The row decoder/word line driver 2 a drives the word line and alater-to-be-described select gate line of the cell array 1. The pagebuffer 3 includes a one page portion of sense amplifier circuits andlatch circuits. A one page portion of read data stored by the pagebuffer 3 is sequentially column selected by the column decoder 2 b to beoutputted to an external I/O terminal via the I/O buffer 9. Write datasupplied from the I/O terminal is selected by the column decoder 2 b tobe loaded into the page buffer 3. The page buffer 3 is loaded with a onepage portion of write data. Row and column address signals are inputtedvia the I/O buffer 9 and transferred to the row decoder 2 a and columndecoder 2 b, respectively. The row address register 5 a stores an eraseblock address in the case of a data erase, and stores a page address inthe case of the data write/read. The column address register 5 b isinputted with a leading column address for loading write data beforestart of the write sequence, or a leading column address for the readsequence. The column address register 5 b stores the inputted columnaddress until a write enable signal /WE or a read enable signal /RE istoggled by a certain condition.

The logic control circuit 6 controls input of a command or an address,and input/output of data, based on control signals such as a chip enablesignal /CE, a command latch enable signal CLE, an address latch enablesignal ALE, the write enable signal /WE, the read enable signal /RE, anda write protect signal /WP. The sequence control circuit 7 receives acommand from the logic control circuit 6 and controls the writesequence, the erase sequence, and the read sequence based on thiscommand. The voltage generating circuit 8 is controlled by the sequencecontrol circuit 7 to generate certain voltages required for variousoperations.

The controller 11 controls the read sequence and the write sequence byconditions appropriate to a current write state of the NAND chip 10.Note that part of the read sequence and the write sequence may also becontrolled by the control unit of the NAND chip 10.

Next, the cell array 1 will be described.

FIG. 2 is a circuit diagram of the cell array of the nonvolatilesemiconductor memory device according to the present embodiment.

The cell array 1 includes: word lines WL<0> to WL<N−1>, select gatelines SGL<0> and SGL<1>, and a source line SL extending in the rowdirection; bit lines BL<0> to BL<M−1> extending in the column direction;and cell strings CS<0> to CS<M−1> provided corresponding to each of thebit lines BL<0> to BL<M−1>. Each of the cell strings CS includes Nmemory cells MC<0> to MC<N−1> connected in series, and select gatesSG<0> and SG<1> connected to both ends of these series-connected memorycells MC. Each of the memory cells MC is configured from a transistorhaving a structure in which a floating gate, acting as a chargeaccumulation layer, and a control gate are stacked, via an insulatingfilm, on a well (sometimes also referred to below as “cell well”) of asemiconductor substrate. Moreover, the select gate SG is configured froma transistor having a structure in which a gate is stacked, via aninsulating film, on a well of the semiconductor substrate. Note that atransistor having a structure similar to that of the memory cell MC canbe utilized in the select gate SG, by short-circuiting the floating gateand the control gate.

A source of the select gate SG<0> is connected to the source line SL. Adrain of the select gate SG<1> is connected to one of the bit linesBL<0> to BL<M−1>. Control gates of the memory cells MC<0> to MC<N−1> areconnected to the word lines WL<0> to WL<N−1>. Gates of the select gatesSG<0> and SG<1> are connected to the select gate lines SGL<0> andSGL<1>.

In the above-described configuration, the M cell strings CS aligned inthe row direction configure one block BLK. The cell array 1 includes Lblocks BLK<0> to BLK<L−1> aligned in the column direction. The dataerase of the flash memory is performed in a unit of this block.

The word line WL and the select gate line SGL are driven by the rowdecoder 2 a. Moreover, each of the bit lines BL is connected to a senseamplifier circuit SA of the page buffer 3.

Next, data storage of the memory cell MC will be described.

FIG. 3 is a view showing threshold voltage distributions of the memorycell of the nonvolatile semiconductor memory device according to thepresent embodiment. FIG. 3 shows the case of 3 bits per cell.

The memory cell MC stores a plurality of data by a plurality ofdifferent threshold voltage distributions, in a nonvolatile manner. Inthe case of 3 bits per cell, each of the memory cells MC has eightthreshold voltage distributions, that is, in order from a low voltageside, threshold voltage distributions of an ER level, an A level, a Blevel, a C level, a D level, an E level, an F level, and a G level, andrespectively allocates to these eight threshold voltage distributions‘111’, ‘011’, ‘001’, ‘000’, ‘010’, ‘110’, ‘100’, and ‘101’ to store3-bit data. A threshold voltage Vth of the memory cell MC is determinedby the number of electrons stored by the floating gate. A state of an ERlevel memory cell is sometimes also referred to below as “erase state”,and a state of an A level through G level memory cell is sometimes alsoreferred to below as “program state”.

It should be noted that although each of the embodiments will bedescribed below assuming the case of 3 bits per cell, each of theembodiments may be applied also in the case of 1 bit per cell or 2 ormore bits per cell.

Hereafter, a method of operating the nonvolatile semiconductor memorydevice will be described.

As previously mentioned, the data write/erase/read on the memory cell isachieved by a series of processes called a sequence. The write sequenceis configured from two operations, that is, a program operation and aprogram verify operation. The erase sequence is configured from an eraseoperation and an erase verify operation. The read sequence is configuredfrom a read operation. Accordingly, each of the operations in thesesequences will be described simply below.

First, the program operation of the present embodiment will bedescribed.

FIG. 4 is a view showing a bias state of the cell array during theprogram operation in the nonvolatile semiconductor memory deviceaccording to the present embodiment. FIG. 4 is an example of the casewhere the memory cell MC<N−3> is assumed to be a selected memory cell.

The program operation is an operation causing a memory cell MC in theerase state to undergo transition to the program state.

In the case of causing the memory cell MC to undergo transition to theprogram state, in other words, in the case of permitting a program onthe memory cell MC, the cell well is set to, for example, a voltageVcpwell=0 V, the select gate line SGL<0> is applied with, for example, 0V, the select gate line SGL<1> is applied with, for example, a powersupply voltage Vdd, and the bit line BL is applied with, for example, 0V. In addition, an unselected word line WL is applied with a passvoltage Vpass (for example, 10 V), and a selected word line WL<N−3> isapplied with a program voltage Vpgm (for example, 20 V). Hence, a largepotential difference occurs between the cell well and the selected wordline WL<N−3>, and electrons are injected into the floating gate of theselected memory cell MC<N−3>. As a result, the threshold voltage Vth ofthe selected memory cell MC<N−3> rises, whereby the selected memory cellMC<N−3> attains the program state.

In the case of not causing the memory cell MC to undergo transition tothe program state, in other words, in the case of inhibiting the programon the memory cell MC, the select gate line SGL<0> is applied with, forexample, 0 V, the select gate line SGL<1> is applied with the powersupply voltage Vdd, and the bit line BL is applied with, for example, 3V. In addition, the unselected word line WL is applied with the passvoltage Vpass, and the selected word line WL<N−3> is applied with theprogram voltage Vpgm (for example, 20 V). In this case, the voltageVcpwell of the cell well rises to a certain inhibit voltage Vinhibit dueto the influence of coupling with the word line WL. Hence, a largepotential difference does not occur between the cell well and theselected word line WL<N−3>, and injection of electrons into the floatinggate of the selected memory cell MC<N−3> is inhibited. As a result, theselected memory cell MC<N−3> is maintained unchanged in the erase state,without its threshold voltage Vth undergoing transition.

Next, the erase operation of the present embodiment will be described.

FIG. 5 is a view showing a bias state of the cell array during the eraseoperation in the nonvolatile semiconductor memory device according tothe present embodiment.

The erase operation is an operation causing a memory cell MC to undergotransition to the erase state.

In the case of causing the memory cell MC to undergo transition to theerase state, the select gate lines SGL<0> and SGL<1> and the bit line BLare set to a floating state. In addition, the cell well is set to anerase voltage Vcpwell=Vera (for example, 15 to 20 V), and all of theword lines WL are applied with a control voltage Viso (for example, 0.5V). Hence, electrons are extracted from the floating gate of all of thememory cells MC. As a result, the threshold voltage Vth of all of thememory cells MC lowers, whereby all of the memory cells MC attain theerase state.

Note that the control voltage employed in the erase operation may beViso=0 V. However, applying a positive voltage as the control voltageViso as in the example of FIG. 5 makes it possible to improve cut-offcharacteristics of a transfer gate-dedicated transistor supplying thecontrol voltage Viso provided between the row decoder/word line driver 2a and each of the blocks BLK. As a result, the transfer-dedicatedtransistor corresponding to an unselected block BLK can be cut off morereliably than in the case where the control voltage is Viso=0 V, hence amistaken erase of the unselected block BLK can be suppressed.

Next, the read operation of the present embodiment will be described.

FIG. 6 is a view showing a bias state of the cell array during the readoperation in the nonvolatile semiconductor memory device according tothe present embodiment. FIG. 6 is an example of the case where thememory cell MC<N−3> is assumed to be the selected memory cell.

In the case of reading data from the memory cell MC, the bit line BL ispre-charged to the power supply voltage Vdd, the source line SL isapplied with, for example, 0 V, the select gate lines SGL<0> and SGL<1>and the unselected word line WL are applied with a read voltage Vread(for example, 4.5 V), and the selected word line WL<N−3> is applied witha reference voltage Vref (for example, 0 V). As a result, if thethreshold voltage of the selected memory cell MC<N−3> is Vth<0 V, thenall of the transistors of the cell string CS including the selectedmemory cell MC<N−3> attain an on state, and a cell current Icell flowsfrom the bit line BL to the source line SL. On the other hand, if thethreshold voltage of the selected memory cell MC<N−3> is Vth>0 V, thenthe transistor of the selected memory cell MC<N−3> attains an off state,hence the cell current Icell does not flow in the cell string CS. Thecontrol unit detects presence/absence of the cell current Icell flowingin the bit line BL by the sense amplifier circuit SA, therebydetermining the threshold voltage Vth of the memory cell MC.

Next, the program verify operation of the present embodiment will bedescribed.

The program verify operation is the same as the above-described readoperation excluding the selected word line WL being applied with averify voltage Vvfy (for example 0.5 V). Now, the verify voltage Vvfy isa voltage of a lower limit of the threshold voltage distribution of theprogram state. Employing this verify voltage Vvfy makes it possible tofind out whether the threshold voltage of the memory cell MC isVth>Vvfy, whereby it can be confirmed whether the memory cell MC hasundergone transition to the program state.

Next, the erase verify operation of the present embodiment will bedescribed.

The erase verify operation is an operation confirming whether all of thememory cells MC of the block BLK have been caused to undergo transitionto the erase state by the erase operation.

FIG. 7 is a view showing a bias state of the cell array during the eraseverify operation in the nonvolatile semiconductor memory deviceaccording to the present embodiment.

It is possible to employ, for example, a so-called negative sensingsystem erase verify operation in confirmation of whether the memory cellMC is in the erase state. In other words, the bit line BL is pre-chargedto the power supply voltage Vdd, and the source line SL is applied witha positive voltage (for example, 1.0 V) having the same magnitude as anerase verify voltage Vevfy (for example, −1.0 V). Now, the erase verifyvoltage Vevfy is a voltage of an upper limit of the threshold voltagedistribution of the erase state. In addition, the select gate linesSGL<0> and SGL<1> are applied with the read pass voltage Vread, and allof the word lines WL are applied with, for example, 0 V as a referencevoltage. As a result, if the threshold voltage of all of the memorycells MC is Vth<Vevfy, then all of the transistors of the cell string CSattain an on state, and a cell current Icell flows from the bit line BLto the source line SL. On the other hand, if the threshold voltage of atleast some of the memory cells MC is Vth>Vevfy, then the transistors ofsaid memory cells MC attain an off state, hence the cell current Icelldoes not flow in the cell string CS. The control unit detectspresence/absence of the cell current Icell flowing in the bit line BL bythe sense amplifier circuit SA, whereby it can be confirmed whether allof the memory cells MC have undergone transition to the erase state.

Next, an example of a 3-bit data write to the memory cell MC whenemploying the above-described program operation, will be described.

FIG. 8 is a view showing a state of transition of the threshold voltagedistributions of the memory cell during the write sequence in thenonvolatile semiconductor memory device according to the presentembodiment.

In this example, 3-bit data is written by executing three stages ofwrite steps on the memory cell MC in the erase state.

In an initial first stage write step (“1st” in FIG. 8, sometimes alsoreferred to as “first write step”), an ER level memory cell MC is causedto undergo transition to an intermediate level. The intermediate levelhas four levels specified therein, that is, from a low voltage side to ahigh voltage side, an LM0 level through LM3 level. If the memory cell MCis finally to be set to the ER level through C level, its thresholdvoltage Vth is maintained unchanged at the ER level. On the other hand,if the memory cell MC is finally to be set to the D level through Glevel, its threshold voltage Vth is caused to undergo transition fromthe ER level to an LM0 level through LM3 level, respectively.

In a following second stage write step (“Foggy” in FIG. 8, sometimesalso referred to as “foggy write step”), a coarse program causing the ERlevel or intermediate level memory cell MC to undergo transition to afoggy level, is performed. The foggy level is a threshold voltagedistribution whose width is broader than a level (fine level) finally tobe set, and has seven levels specified therein, that is, from a lowvoltage side to a high voltage side, an Af level through Gf level. Ifthe memory cell MC is finally to be set to the ER level, its thresholdvoltage Vth is maintained unchanged at the ER level. On the other hand,if the memory cell MC is finally to be set to the A level through Clevel, its threshold voltage Vth is caused to undergo transition fromthe ER level to the Af level through Cf level, respectively. Moreover,if the memory cell MC is finally to be set to the D level through Glevel, its threshold voltage Vth is caused to undergo transition fromthe LM0 level through LM3 level to the Df level through Gf level,respectively.

In a final third stage write step (“Fine” in FIG. 8, sometimes alsoreferred to as “fine write step”), a fine program causing the ER levelor foggy level memory cell MC to undergo transition to a final finelevel, in other words, the ER level and A level through G level, isperformed. If the memory cell MC is to be set to the ER level, itsthreshold voltage Vth is maintained unchanged at the ER level. On theother hand, if the memory cell MC is to be set to the A level through Glevel, the memory cell MC on a lower tail side of the Af level throughGf level is programmed to narrow a distribution width of each of thelevels. As a result, the memory cell MC is set with the final narrowdistribution width level A through level G.

Next, an example of a write sequence of pages in the block BLK will bedescribed.

In the case of a NAND type flash memory, data is written in order, inunits of the page, from a source line SL side to a bit line BL side ofthe block BLK. However, in the case of simply completing the writesequence on one page, and then starting the write operation on the nextpage in the manner of first write step→foggy write step→fine write stepon page<0> (where page<n> is assumed to refer to the page configuredfrom the plurality of memory cells MC connected to the word line WL<n>),first write step→foggy write step→fine write step on page<1> . . . , itsometimes also occurs that the influence of coupling with the adjacentword line WL cannot be fully compensated, leading to a problem ofdisturbance where the threshold voltage Vth of a write-completed memorycell MC varies.

Accordingly, in the present embodiment, the data write is advanced by asequence of the kind described below, for example.

FIG. 9 is a view showing the write sequence of pages in the data writeof the nonvolatile semiconductor memory device according to the presentembodiment. FIG. 9 is an example of the case of storing 256 bits per onecell string.

In the case of FIG. 9, the data write is executed in an order of firstwrite step on page<0>→first write step on page<1>→foggy write step onpage<0>→first write step on page<2>→foggy write step on page<1>→finewrite step on page<0> . . . first write step on page<85>→foggy writestep on page<84>→fine write step on page<83>→foggy write step onpage<85>→fine write step on page<84>→fine write step on page<85>. Inthis case, even if a write step on page<n+1> causes the thresholdvoltage Vth of the memory cell MC of page<n> to end up varying, a writestep on page<n> is later executed. As a result, the influence of thewrite step on page<n+1> can be canceled out afterwards. In other words,employing the write sequence of pages shown in FIG. 9 makes it possibleto reduce the influence of coupling with the word line WL during thewrite step of the adjacent page.

The above represents the basic method of operating the nonvolatilesemiconductor memory device according to the present embodiment.However, simply employing the above-described method of operating maylead to the following kinds of problems.

FIG. 10 is a view showing a state of transition of the threshold voltagedistribution of the memory cell during the read operation in thenonvolatile semiconductor memory device according to the presentembodiment.

Here, the following case is considered, that is, the case where data isnewly added to page<n1> (where n1 is an integer of 1 to N−1) throughpage<N−1> of a block BLK<11> (where 11 is an integer of 0 to L−1)(sometimes also referred to below as “target block”) that already hasvalid data written to page<0> through page<n1−1> thereof. This iscorresponded to by, for example, the case where when writing a group ofdata to page<0> through page<N−1> of the target block BLK<11>, a commandof suspend is issued from the controller 11 at a time point when thewrite has proceeded to page<n1−1> to suspend the data write.

It is assumed that under these circumstances, during data writesuspension, a read of the valid data (referred to below as “existingdata”) already stored in page<0> through page<n1−1> of the target blockBLK<11> is executed. In this case, as previously mentioned, theunselected word line WL in the target block BLK<11> is applied with theread voltage Vread, but sometimes this read voltage Vread exerts aninfluence whereby the threshold voltage Vth of the unselected memorycell MC rises. Moreover, these unselected memory cells MC include alsoan erase state memory cell MC belonging to page<n1> through page<N−1>prior to the data write. In other words, as shown by the arrow of FIG.10, the threshold voltage distribution of the memory cell MC of page<n1>through page<N−1> sometimes ends up extending on an upper tail side.Moreover, when a command of resume is issued from the controller 11whereby the data write is resumed, these memory cells MC whose thresholdvoltage Vth has ended up rising undergo execution of a data writeassuming them to be in the erase state, hence it becomes easier for amistaken write to Occur.

Accordingly, in the present embodiment, the data write is devised asfollows.

FIG. 11 is a flowchart of the data write in the nonvolatilesemiconductor memory device according to the present embodiment. FIG. 11is a flow after the data erase has been executed on the target block.

First, in step S101, the control unit writes the group of data in orderfrom page<0> of the target block BLK<11>.

Now, when the command of suspend is issued from the controller 11, thecontrol unit suspends the data write. At this time point, data (existingdata) is assumed to have been written from page<0> through page<n1−1> ofthe target block BLK<11>. During data write suspension, processing ofthe likes of the read on the existing data on page<0> through page<n1−1>of the target block BLK<11>, is performed (step S102). Then, when theprocessing finishes, the command of resume is issued from the controller11.

Following this, the control unit receives the command of resume toresume the data write, but in following steps S103 and S104, performspre-processing for that resumption. This pre-processing is a processingthat determines the influence that the read voltage Vread exerts on thepre-data write pages. In step S103, a data read adopting as a referencepage a specific page of pre-data write page<n1> through page<N−1> in thetarget block BLK<11>, is performed, and the number Nca of memory cellshaving a threshold voltage Vth higher than a specific value (forexample, the erase verify voltage Vevfy which is an upper limit value ofthe ER level shown in FIG. 10) in this reference page, is counted. Infollowing step S104, if the number Nca of memory cells is less than acertain reference number Ncr, then processing is shifted to step S105.On the other hand, if the number Nca of memory cells is the referencenumber Ncr or more, then processing is shifted to step S106.

Following step S105 is a step executed when the influence of the readvoltage Vread on pre-data write page<n1> through page<N−1> was small. Inthis step S105, the control unit writes remaining data (sometimes alsoreferred to below as “additional data”) to page<n1> through page<N−1> ofthe target block BLK<11>, as a continuation of the suspended data write.

On the other hand, step S106 and steps S107 and S108 following step S106are steps executed when the influence of the read voltage Vread onpre-data write page<n1> through page<N−1> is large.

In step S106, the control unit shifts processing selecting one of twodifferent data write steps S107 and S108, in view of processingefficiency due to the likes of kind or size of the existing data and theadditional data.

In step S107, the control unit writes only the additional data in ablock BLK<12> (where 12 is an integer of 0 to L−1 excluding 11)(sometimes also referred to below as “substitute block”) different fromthe target block BLK<11>. This step S107 is effective, for example, whenthe existing data and the additional data are code of a program, and soon, where size is comparatively small and there are few occasions ofbatch reading.

On the other hand, in step S108, the control unit, in addition towriting the additional data to the substitute block BLK<12>, alsofreshly rewrites the existing data already written to the target blockBLK<11>, to the substitute block BLK<12>. Moreover, the control unitdestroys the existing data of the target block BLK<11>. This step S108is effective, for example, when the existing data and the additionaldata are graphics data, and so on, where size is comparatively large andthere are many occasions of batch reading.

Note that in steps S105, S107, and S108, when a suspend/resume commandis issued during processing, processing similar to that of steps S103and S104 adopting the mid-data write block BLK as the target block, isperformed.

The above is the flow of the data write of the present embodiment.

In the data write shown in FIG. 11, steps S103 and S104 detect thethreshold voltage Vth of the pre-data write memory cells MC of thetarget block BLK<11>, thereby predicting ease of occurrence of amistaken write when the additional data is written to the target blockBLK<11>. Moreover, when it is determined that a mistaken write is easilygenerated, steps S107 and S108 write the additional data to thesubstitute block BLK<12>, thereby avoiding generation of a mistakenwrite occurring when the additional data is added to the target blockBLK<11>.

Next, variations of the write operation described using the flowchart ofFIG. 11, will be referred to.

First, a method of selecting the reference page instep S103 will bedescribed.

As previously mentioned, steps S103 and S104 of the data write shown inFIG. 11 are steps determining the influence that the read voltage Vreadexerts on the pre-data write pages. Considering this point only, sincethe word lines WL corresponding to each of the unselected pages areequally applied with the read voltage Vread, then any of the pages maybe selected as the reference page, provided it is a pre-data write page.For example, page<N−1> on which the data write is last performed in thetarget block BLK may be fixed as the reference page. In this case, thereis no need to change the reference page according to a state of progressof the data write, hence control can be performed simply.

Moreover, the program voltage Vpgm applied to the selected word line WLduring the data write also exerts an influence on the threshold voltageVth of the unselected memory cell MC, and in view of this influence, itis also possible to adopt as the reference page a page situated as muchas possible to the source line SL side of the pre-data write pages, thatis, a page closer to the pages where data has been written. For example,in the case that when the data write is advanced in the sequence of FIG.9, the most recent write step last executed before data write suspensionwas on page<n2> (where n2 is an integer of 0 to n1−1), it is possible toselect page<n2+3> as the reference page. If selection is made in thisway, it is possible to adopt as the reference page a page which iscertainly pre-data write, and is adjacent to the selected page topossibly receive the influence of the program voltage Vpgm, irrespectiveof what stage of write step the most recent write step was. Generally,in the case of executing by M times (where M is an integer of 1 or more)of the write step for each memory cell MC and when the most recent writestep was on page<n2>, it is possible to select page<n2+M> as thereference page. This method of selecting makes it possible to morereliably determine the state of transition of the threshold voltage Vthand appropriately avoid a mistaken write, compared to when page<N−1> isalways adopted as the reference page.

Furthermore, when it is desired to appropriately avoid a mistaken write,the reference page may be selected in view of what stage the most recentwrite step is. In other words, in the case that when the data write isadvanced in the sequence of FIG. 9, the most recent write step was onpage<n2> and was a first write step, the most recent write step was onpage<n2> and was a foggy write step, and the most recent write step wason page<2> and was a fine write step, it is possible to selectpage<n2+1>, page<n2+2>, and page<n2+3>, respectively, as the referencepage. If selection is made in this way, it is possible to adopt as thereference page a page which is certainly pre-data write, and is adjacentto the selected page to be closest to the selected page receiving theinfluence of the program voltage Vpgm, inconsideration of what stage ofwrite step the most recent write step was. Generally, in the case ofexecuting by M times of the write step for each memory cell MC and whenthe most recent write step was an m-th stage (where m is an integer of 1to M) write step of page<n2>, it is possible to select page<n2+m> as thereference page. This method of selecting makes it possible to morereliably determine the state of transition of the threshold voltage Vthand appropriately avoid a mistaken write, compared to when page<n2+M> isadopted as the reference page.

The above-described method of selecting the reference page can beselected in view of complexity of processing or specifications such aserror processing capacity included in the nonvolatile semiconductormemory device.

Note that when the most recent write step is on a page close to the bitline BL and the reference page cannot be selected by the above-describedmethod of selecting, steps S103, S104, and S106 through S108 may beomitted.

Next, the reference number Ncr will be described.

The reference number Ncr can be determined in view of error processingcapacity included in the nonvolatile semiconductor memory device, and soon. Moreover, considering that endurance of the memory cell MC changesby the number of times of data write/erase on the target block, it isalso possible to prepare a plurality of reference numbers Ncr accordingto the number of times of data write/erase.

As described above, in the case of the data write of the presentembodiment, it is possible to detect the threshold voltage of thepre-data write memory cells to predict how easily a mistaken writeoccurs, and thereby suppress a mistaken write occurring due to a laterresumed data write. In other words, the present embodiment makes itpossible to provide a nonvolatile semiconductor memory device wherethere are few mistaken writes of data.

Note that the description above proceeded assuming the case where thedata write is suspended in the process of writing a group of data andthe remaining data is added from mid-way in the target block. However,the present invention is not limited to this case, and provided thatdata is added to a block already written with valid data, the presentembodiment may be applied even when the existing data and the additionaldata are completely different data. Moreover, described above was thecase of employing a 3 bits per cell memory cell. However, the presentembodiment can be applied even in the case of a 1 bit per cell memorycell, a 2 or more bits per cell memory cell, or where these are mixed.Regarding these points, the same applies also to the embodiments below.

Second Embodiment

The first embodiment detected the threshold voltage of the memory cellsof the reference page, thereby determining how much the thresholdvoltage of the pre-data write memory cells has changed, to predict easeof occurrence of a mistaken write. In contrast, the second embodimentestimates how much the threshold voltage of the pre-data write memorycells has changed by the number of times of read of the existing data,to predict ease of occurrence of a mistaken write.

FIG. 12 is a flowchart of a data write in a nonvolatile semiconductormemory device according to the second embodiment. FIG. 12 is a flowafter the data erase has been executed on the target block.

Initial step S201, following suspend, step S202, and resume are similarto step S101, following suspend, step S102, and resume of FIG. 11.

In following step S203, the influence that the read voltage Vread exertson the pre-data write pages is determined, similarly to in steps S103and S104 of FIG. 11. However, in step S203, the control unit determineswhether the number of times Nra of read of the existing data stored inpage<0> through page<n1−1> of the target block BLK<11> executed duringdata write suspension is less than a certain reference number of timesNrr. If the number of times Nra of read is less than the referencenumber of times Nrr, in other words, if there are few data reads on theexisting data during data write suspension, and transition of thethreshold voltage Vth of the memory cells MC of pre-data write page<n1>through page<N−1> is thought to be small, then processing is shifted tostep S204. On the other hand, if the number of times Nra of read is thereference number of times Nrr or more, in other words, if there are manydata reads on the existing data during data write suspension, andtransition of the threshold voltage Vth of the memory cells MC ofpre-data write page<n1> through page<N−1> is thought to be large, thenprocessing is shifted to step S205.

In following steps S204 through S207, processing similar to that insteps S105 through S108 of FIG. 11 is performed.

Note that in steps S204, S206, and S207, when a suspend/resume commandis issued during processing, processing similar to that of step S203adopting the mid-data write block BLK as the target block, is performed,similarly to in the first embodiment.

The above is the flow of the data write of the present embodiment.

Note that the reference number of times Nrr can be determined in view oferror processing capacity included in the nonvolatile semiconductormemory device, and so on. Moreover, considering that endurance of thememory cell MC changes by the number of times of data write/erase on thetarget block, it is also possible to prepare a plurality of referencenumbers of times Nrr according to the number of times of datawrite/erase.

As described above, in the case of the data write of the presentembodiment, it is possible to predict how easily a mistaken write occursbased on the number of times of read of the existing data, and therebysuppress a mistaken write occurring due to a later resumed data write.In other words, the present embodiment makes it possible to provide anonvolatile semiconductor memory device where there are few mistakenwrites of data, similarly to the first embodiment.

Third Embodiment

In a third embodiment, a data write combining the data writes of thefirst and second embodiments will be described.

FIG. 13 is a flowchart of a data write in a nonvolatile semiconductormemory device according to the third embodiment. FIG. 13 is a flow afterthe data erase has been executed on the target block.

Initial step S301, following suspend, step S302, and resume are similarto step S101, following suspend, step S102, and resume of FIG. 11.

In following step S303, processing similar to that in step S203 of FIG.12 is performed. In other words, in step S303, the control unitdetermines whether the number of times Nra of read of the existing datastored in page<0> through page<n1−1> of the target block BLK<11>executed during data write suspension is less than a certain referencenumber of times Nrr (first requirement). If the number of times Nra ofread is less than the reference number of times Nrr, then processing isshifted to step S304. On the other hand, if the number of times Nra ofread is the reference number of times Nrr or more, then processing isshifted to step S307.

In following steps S304 and S305, processing similar to that in stepsS103 and S104 of FIG. 11 is performed. In other words, the number Nca ofmemory cells having a threshold voltage Vth higher than a specific valuebelonging to a reference page is counted, and it is determined whetherthe number Nca of memory cells is less than a certain reference numberNcr (second requirement). If the number Nca of memory cells is less thanthe reference number Ncr, then processing is shifted to step S306. Onthe other hand, if the number Nca of memory cells is the referencenumber Ncr or more, then processing is shifted to step S307.

In following steps S306 through S309, processing similar to that insteps S105 through S108 of FIG. 11 is performed.

Note that in steps S306, S308, and S309, when a suspend/resume commandis issued during processing, processing similar to that of steps S303through S305 adopting the mid-data write block BLK as the target block,is performed, similarly to in the first and second embodiments.

The above is the flow of the data write of the present embodiment.

Note that the reference number of times Nrr and the reference number Ncrcan be determined in view of error processing capacity included in thenonvolatile semiconductor memory device, and so on, similarly to in thefirst and second embodiments. Moreover, considering that endurance ofthe memory cell MC changes by the number of times of data write/erase onthe target block, it is also possible to prepare a plurality ofreference numbers of times Nrr and reference numbers Ncr according tothe number of times of data write/erase.

As described above, in the case of the data write of the presentembodiment, by performing a determination based not only on detection ofthe threshold voltage of the pre-data write memory cells similar to thatof the first embodiment, but also on the number of times of read of theexisting data similar to that of the second embodiment, it is possibleto more accurately predict how easily a mistaken write occurs, comparedto in the first and second embodiments. In other words, the presentembodiment makes it possible to provide a nonvolatile semiconductormemory device where there are fewer mistaken writes of data, compared toin the first and second embodiments.

[Others]

While certain embodiments of the inventions have been described, theseembodiments have been presented by way of example only, and are notintended to limit the scope of the inventions. Indeed, the novel methodsand systems described herein may be embodied in a variety of otherforms; furthermore, various omissions, substitutions and changes in theform of the methods and systems described herein may be made withoutdeparting from the spirit of the inventions. The accompanying claims andtheir equivalents are intended to cover such forms or modifications aswould fall within the scope and spirit of the inventions.

What is claimed is:
 1. A nonvolatile semiconductor memory device,comprising: a cell array including a source line, a plurality of bitlines, a plurality of word lines intersecting the plurality of bitlines, and a plurality of cell strings electrically connected betweenthe source line and the plurality of bit lines, each of the cell stringsbeing configured from a plurality of memory cells connected in series toeach be connected to one of the word lines; and a control unit thatperforms a data write/erase/read on the memory cells, the cell arraybeing divided into a plurality of blocks including a target block, eachof the blocks including first through N-th pages (where N is an integerof 2 or more), each of the pages being configured by a plurality of thememory cells connected to one of the word lines, the control unitexecuting the data write/read in a unit of the page, and executing thedata erase in a unit of the block, and the control unit, in the datawrite, determining at least one of: a first requirement that the numberof times of the data read on first through n1-th pages (where n1 is aninteger of 1 to N−1) of the target block executed after the most recentdata erase on the target block, is less than a reference number oftimes; and a second requirement that the number of memory cells whosethreshold voltage is higher than a reference voltage, of the pluralityof memory cells of a reference page of n1+1-th through N-th pages of thetarget block, is less than a reference number, and when the determinedrequirement is satisfied, writing additional data to the n1+1-th throughN-th pages of the target block.
 2. The nonvolatile semiconductor memorydevice according to claim 1, wherein the control unit, in the datawrite, when the determined requirement is not satisfied, writes theadditional data to a substitute block different from the target block,of the plurality of blocks.
 3. The nonvolatile semiconductor memorydevice according to claim 2, wherein the control unit, in the datawrite, when the determined requirement is not satisfied, writes alsoexisting data stored by the first through n1-th pages of the targetblock along with write of the additional data, to the substitute block,based on at least one of size and kind of the additional data.
 4. Thenonvolatile semiconductor memory device according to claim 1, wherein atleast some of the plurality of memory cells store data of two or morebits.
 5. The nonvolatile semiconductor memory device according to claim4, wherein the control unit, in the data write, executes on each of thememory cells a plurality of write steps causing a threshold voltage ofthe memory cell to undergo transition to a desired value in stages, andthe write step of an identical stage is executed in order of the firstpage, the second page, . . . , the N-th page in each of the blocks. 6.The nonvolatile semiconductor memory device according to claim 1,wherein the first through N-th pages of each of the blocks are disposedin order from a source line side to a bit line side.
 7. A nonvolatilesemiconductor memory device, comprising: a cell array including a sourceline, a plurality of bit lines, a plurality of word lines intersectingthe plurality of bit lines, and a plurality of cell strings electricallyconnected between the source line and the plurality of bit lines, eachof the cell strings being configured from a plurality of memory cellsconnected in series to each be connected to one of the word lines; and acontrol unit that performs a data write/erase/read on the memory cells,the cell array being divided into a plurality of blocks including atarget block, each of the blocks including first through N-th pages(where N is an integer of 2 or more), each of the pages being configuredby a plurality of the memory cells connected to one of the word lines,the control unit executing the data write/read in a unit of the page,and executing the data erase in a unit of the block, and the controlunit, in the data write, subsequent to a first number of times of thedata read on first through n1-th pages (where n1 is an integer of 1 toN−1) of the target block after the most recent data erase on the targetblock, writing additional data to n1+1-th through N-th pages of thetarget block, and subsequent to a second number of times greater thanthe first number of times of the data read on the first through n1-thpages of the target block after the most recent data erase on the targetblock, not writing the additional data to the n1+1-th through N-th pagesof the target block.
 8. The nonvolatile semiconductor memory deviceaccording to claim 7, wherein the control unit, in the data write,subsequent to the second number of times of the data read on the firstthrough n1-th pages of the target block after the most recent data eraseon the target block, writes the additional data to a substitute blockdifferent from the target block, of the plurality of blocks.
 9. Thenonvolatile semiconductor memory device according to claim 7, whereinthe first number of times is a value less than a reference number oftimes, and the second number of times is a value of the reference numberof times or more.
 10. The nonvolatile semiconductor memory deviceaccording to claim 9, wherein the control unit determines the referencenumber of times based on the number of times of the data write/dataerase on the target block.
 11. A nonvolatile semiconductor memorydevice, comprising: a cell array including a source line, a plurality ofbit lines, a plurality of word lines intersecting the plurality of bitlines, and a plurality of cell strings electrically connected betweenthe source line and the plurality of bit lines, each of the cell stringsbeing configured from a plurality of memory cells connected in series toeach be connected to one of the word lines; and a control unit thatperforms a data write/erase/read on the memory cells, the cell arraybeing divided into a plurality of blocks including a target block, eachof the blocks including first through N-th pages (where N is an integerof 2 or more), each of the pages being configured by a plurality of thememory cells connected to one of the word lines, the control unitexecuting the data write/read in a unit of the page, and executing thedata erase in a unit of the block, and the control unit, after the datawrite on first through n1-th pages (where n1 is an integer of 1 to N−1)of the target block, suspending the data write, and then, when resumingthe data write, executing the data read on a reference page of n1+1-ththrough N-th pages of the target block.
 12. The nonvolatilesemiconductor memory device according to claim 11, wherein the controlunit, when the number of memory cells whose threshold voltage is higherthan a reference voltage, of the plurality of memory cells of thereference page, is a first number, writes additional data to the n1+1-ththrough N-th pages of the target block, and when the number of memorycells whose threshold voltage is higher than the reference voltage, ofthe plurality of memory cells of the reference page, is a second numberlarger than the first number, does not write the additional data to then1+1-th through N-th pages of the target block.
 13. The nonvolatilesemiconductor memory device according to claim 12, wherein the controlunit, when the number of memory cells whose threshold voltage is higherthan the reference voltage, of the plurality of memory cells of thereference page, is the second number, writes the additional data to asubstitute block different from the target block, of the plurality ofblocks.
 14. The nonvolatile semiconductor memory device according toclaim 12, wherein the first number is a value less than a referencenumber, and the second number is a value of the reference number ormore.
 15. The nonvolatile semiconductor memory device according to claim14, wherein the control unit determines the reference number based onthe number of times of the data write/data erase on the target block.16. The nonvolatile semiconductor memory device according to claim 11,wherein the control unit adopts as the reference page the page closestto the page on which the data write has been executed, of pages on whichthe data write has not been executed after the most recent data erase onthe target block.
 17. The nonvolatile semiconductor memory deviceaccording to claim 16, wherein the control unit executes on each of thememory cells M times (where M is an integer of 1 or more) of a writestep causing a threshold voltage of the memory cell to undergotransition to a desired value in stages, executes the write step of anidentical stage in order of the first page, the second page, . . . , theN-th page in each of the blocks, and adopts an n1+M-th page as thereference page.
 18. The nonvolatile semiconductor memory deviceaccording to claim 16, wherein the control unit executes on each of thememory cells M times (where M is an integer of 1 or more) of a writestep causing a threshold voltage of the memory cell to undergotransition to a desired value in stages, executes the write step of anidentical stage in order of the first page, the second page, . . . , theN-th page in each of the blocks, and when a final data write beforesuspension of the data write is on an n2-th page (where n2 is an integerof 1 to n1) and is an m-th stage (where m is an integer of 1 to M) writestep on the n2-th page, adopts an n2+m-th page as the reference page.19. The nonvolatile semiconductor memory device according to claim 11,wherein the control unit adopts as the reference page a page where thedata write is last performed in the target block.
 20. The nonvolatilesemiconductor memory device according to claim 11, wherein the controlunit, when the data write is suspended having executed the data write onthe first through N-th pages after the most recent data erase on thetarget block, omits the data read on the reference page.